Hardware emulators are programmable devices used to verify hardware designs and integrated circuits having very high logic densities (e.g., large numbers of logic gates). A common method of design verification is to use processor-based hardware emulators to emulate the design prior to physically manufacturing the integrated circuit(s) of the hardware. These processor-based emulators sequentially evaluate combinatorial logic levels in the design under verification, starting at the inputs and proceeding to the outputs. Each pass through the entire set of logic levels is known as a cycle; the evaluation of each individual logic level is known as an emulation step.
An exemplary hardware emulator is described in commonly assigned U.S. Pat. No. 6,618,698 entitled “Clustered Processors In An Emulation Engine,” which is hereby incorporated by reference in its entirety. Hardware emulators allow engineers and hardware designers to test and verify the operation of an integrated circuit, an entire board of integrated circuits, or an entire system without having to first physically fabricate the hardware.
The complexity and number of logic gates present on an integrated circuit increases significantly every year. In order to emulate such large (e.g., high gate count) integrated circuits, processor-based hardware emulators now commonly contain hundreds of thousands of processors that must efficiently communicate in the process of emulating the design under verification.
The hardware emulator's processors are generally arranged into groups of processors known as clusters. In a conventional processor-based hardware emulator, each processor cluster has a memory, and each processor in a cluster can access the common area of the shared memory. The processors address the shared memory via an instruction word that is stored in a special instruction memory. This instruction word contains a read address for the data to be evaluated and a Boolean function table that instructs the processor how to evaluate the data. After evaluation, the processor stores the produced result back to the same memory location as indicated by the instruction address.
The amount of memory required by a conventional hardware emulator is directly dependent on the number of processors present in the hardware emulator. Specifically, the hardware emulator must contain memory that is at least equal to the number of processors multiplied by the depth of the instruction memory. The instruction word must contain several address fields to enable the processor to address any location within the memory.
Whenever the evaluation process for the design under verification requires that the processor which belongs to one cluster operates upon the data produced by a processor which belongs to another cluster, such data needs to be first transferred from the shared memory unit of the processors in the producing, or source, cluster to the shared memory unit of the processors in the consuming, or destination, cluster. In some embodiments of a processor-based emulation system, there are as many as 8 processors in a cluster. In other embodiments there are as few as 4 processors. This means that in an emulator system comprised of hundreds of thousands of processors must contain tens of thousands or hundreds of thousands of clusters, interconnected with communication channels.
The communication channels between clusters can be of different physical nature: some may be implemented in silicon die; some in the substrate of a multi-chip module; some in a printed circuit board; and some using electrical or optical cables. Various implementations of communication channels have different degrees of reliability commonly characterized by mean time between failures (MTBF). Commonly, those communication channels implemented on a silicon die exhibit a high degree of reliability, while cable connections are less reliable.
Replacement of a component causing failure of a communication channel, even when possible, requires service action and causes system downtime, thereby increasing the cost of ownership of the emulation system. One way to reduce the frequency of service and maintain system reliability that is known in the prior art is to make a list of failed communication channels, which list is available to the compiler software that maps the design under verification to the emulation system. Based on the information provided by the list, the compiler can avoid failed channels by using alternative routes to pass information between clusters. However, each time a new failed channel is detected, various designs under verification in the system must be recompiled to use the alternative routes. This effectively causes down time of the verification process until recompilation is complete. For the customers owning several emulation systems, such failure or defect maps create asymmetries such that a design compiled for one emulation system can no longer be used with the other emulation systems.
Thus, there is a need in the art for hardware emulation systems with increased reliability of interconnect in view of communication channel failures.